/[VMELinux]/driver/ca91c042.h
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Contents of /driver/ca91c042.h

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Revision 1.7 - (show annotations)
Fri May 14 21:47:37 2004 UTC (15 years, 2 months ago) by jhuggins
Branch: MAIN
CVS Tags: License_change_back_to_GPL_May_2004, HEAD
Changes since 1.6: +30 -59 lines
File MIME type: text/plain
Changed license back to GPL.
Revised copyright year and contact information.
1 // ====================================================================
2 // These VMELinux tools provide Linux access to the VMEbus via the
3 // Tundra Universe PCI/VME bridge.
4 // Copyright (C) 1997-2004 John Huggins and Michael Wyrick
5 //
6 // This program is free software; you can redistribute it and/or modify
7 // it under the terms of the GNU General Public License as published by
8 // the Free Software Foundation; either version 2 of the License, or
9 // (at your option) any later version.
10 //
11 // This program is distributed in the hope that it will be useful,
12 // but WITHOUT ANY WARRANTY; without even the implied warranty of
13 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 // GNU General Public License for more details.
15 //
16 // You should have received a copy of the GNU General Public License
17 // along with this program; if not, write to the Free Software
18 // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 //
20 // Contact the VMELinux project manager with questions at john@johnhuggins.com
21 // ====================================================================
22 //
23 // This software consists of voluntary contributions made by many
24 // individuals on behalf of the VMELinux Project. For more
25 // information on the VMELinux Project, please see
26 // <http://www.vmelinux.org/>.
27 //
28
29 //------------------------------------------------------------------------------
30 // Title: Tundra Universe PCI-VME Kernel Driver
31 // Initial programmer: Michael Wyrick
32 // $Date: 2004/05/14 21:47:37 $
33 // $Author: jhuggins $
34 // $Revision: 1.7 $
35 //------------------------------------------------------------------------------
36 // Purpose: Provide a Kernel Driver to Linux for the Universe I and II
37 // Universe model number ca91c042
38 // Docs:
39 // This driver supports:
40 // Universe
41 // Universe II
42 // Universe II B
43 // Universe II D
44 //-----------------------------------------------------------------------------
45 #ifndef _ca91c042_H
46 #define _ca91c042_H
47
48 //-----------------------------------------------------------------------------
49 // Public Functions
50 //-----------------------------------------------------------------------------
51 // This is the typedef for a VmeIrqHandler
52 typedef void (*TirqHandler)(int vmeirq, int vector, void *dev_id, struct pt_regs *regs);
53 // This is the typedef for a DMA Transfer Callback function
54 typedef void (*TDMAcallback)(int status);
55
56 // Returns the PCI baseaddress of the Universe chip
57 char* Universe_BaseAddr(void);
58 // Returns the PCI IRQ That the universe is using
59 int Universe_IRQ(void);
60
61 char* mapvme(unsigned int pci, unsigned int vme, unsigned int size,
62 int image,int ctl);
63 void unmapvme(char *ptr, int image);
64
65 // Interrupt Stuff
66 void enable_vmeirq(unsigned int irq);
67 void disable_vmeirq(unsigned int irq);
68 int request_vmeirq(unsigned int irq, TirqHandler);
69 void free_vmeirq(unsigned int irq);
70
71 // DMA Stuff
72 void VME_DMA(void* pci, void* vme, unsigned int count, int ctl, TDMAcallback cback);
73 void VME_DMA_LinkedList(void* CmdPacketList,TDMAcallback cback);
74
75 // Misc
76 int VME_Bus_Error(void);
77
78 //-----------------------------------------------------------------------------
79 //
80 //-----------------------------------------------------------------------------
81 #define IRQ_VOWN 0x0001
82 #define IRQ_VIRQ1 0x0002
83 #define IRQ_VIRQ2 0x0004
84 #define IRQ_VIRQ3 0x0008
85 #define IRQ_VIRQ4 0x0010
86 #define IRQ_VIRQ5 0x0020
87 #define IRQ_VIRQ6 0x0040
88 #define IRQ_VIRQ7 0x0080
89 #define IRQ_DMA 0x0100
90 #define IRQ_LERR 0x0200
91 #define IRQ_VERR 0x0400
92 #define IRQ_res 0x0800
93 #define IRQ_IACK 0x1000
94 #define IRQ_SWINT 0x2000
95 #define IRQ_SYSFAIL 0x4000
96 #define IRQ_ACFAIL 0x8000
97
98 //-----------------------------------------------------------------------------
99 //
100 //-----------------------------------------------------------------------------
101 // See Page 2-77 in the Universe User Manual
102 typedef struct
103 {
104 unsigned int dctl; // DMA Control
105 unsigned int dtbc; // Transfer Byte Count
106 unsigned int dlv; // PCI Address
107 unsigned int res1; // Reserved
108 unsigned int dva; // Vme Address
109 unsigned int res2; // Reserved
110 unsigned int dcpp; // Pointer to Numed Cmd Packet with rPN
111 unsigned int res3; // Reserved
112 } TDMA_Cmd_Packet;
113
114 //-----------------------------------------------------------------------------
115 // Below here is normaly not used by a user module
116 //-----------------------------------------------------------------------------
117 #define DMATIMEOUT 2*HZ;
118
119 // Define for the Universe
120 #define SEEK_SET 0
121 #define SEEK_CUR 1
122
123 #define CONFIG_REG_SPACE 0xA0000000
124
125 #define PCI_SIZE_8 0x0001
126 #define PCI_SIZE_16 0x0002
127 #define PCI_SIZE_32 0x0003
128
129 #define IOCTL_SET_CTL 0xF001
130 #define IOCTL_SET_BS 0xF002
131 #define IOCTL_SET_BD 0xF003
132 #define IOCTL_SET_TO 0xF004
133 #define IOCTL_PCI_SIZE 0xF005
134 #define IOCTL_SET_MODE 0xF006
135 #define IOCTL_SET_WINT 0xF007 // Wait for interrupt before read
136
137 #define PCI_ID 0x0000
138 #define PCI_CSR 0x0004
139 #define PCI_CLASS 0x0008
140 #define PCI_MISC0 0x000C
141 #define PCI_BS 0x0010
142 #define PCI_MISC1 0x003C
143
144 #define LSI0_CTL 0x0100
145 #define LSI0_BS 0x0104
146 #define LSI0_BD 0x0108
147 #define LSI0_TO 0x010C
148
149 #define LSI1_CTL 0x0114
150 #define LSI1_BS 0x0118
151 #define LSI1_BD 0x011C
152 #define LSI1_TO 0x0120
153
154 #define LSI2_CTL 0x0128
155 #define LSI2_BS 0x012C
156 #define LSI2_BD 0x0130
157 #define LSI2_TO 0x0134
158
159 #define LSI3_CTL 0x013C
160 #define LSI3_BS 0x0140
161 #define LSI3_BD 0x0144
162 #define LSI3_TO 0x0148
163
164 #define LSI4_CTL 0x01A0
165 #define LSI4_BS 0x01A4
166 #define LSI4_BD 0x01A8
167 #define LSI4_TO 0x01AC
168
169 #define LSI5_CTL 0x01B4
170 #define LSI5_BS 0x01B8
171 #define LSI5_BD 0x01BC
172 #define LSI5_TO 0x01C0
173
174 #define LSI6_CTL 0x01C8
175 #define LSI6_BS 0x01CC
176 #define LSI6_BD 0x01D0
177 #define LSI6_TO 0x01D4
178
179 #define LSI7_CTL 0x01DC
180 #define LSI7_BS 0x01E0
181 #define LSI7_BD 0x01E4
182 #define LSI7_TO 0x01E8
183
184 #define SCYC_CTL 0x0170
185 #define SCYC_ADDR 0x0174
186 #define SCYC_EN 0x0178
187 #define SCYC_CMP 0x017C
188 #define SCYC_SWP 0x0180
189 #define LMISC 0x0184
190 #define SLSI 0x0188
191 #define L_CMDERR 0x018C
192 #define LAERR 0x0190
193
194 #define DCTL 0x0200
195 #define DTBC 0x0204
196 #define DLA 0x0208
197 #define DVA 0x0210
198 #define DCPP 0x0218
199 #define DGCS 0x0220
200 #define D_LLUE 0x0224
201
202 #define LINT_EN 0x0300
203 #define LINT_STAT 0x0304
204 #define LINT_MAP0 0x0308
205 #define LINT_MAP1 0x030C
206 #define VINT_EN 0x0310
207 #define VINT_STAT 0x0314
208 #define VINT_MAP0 0x0318
209 #define VINT_MAP1 0x031C
210 #define STATID 0x0320
211 #define V1_STATID 0x0324
212 #define V2_STATID 0x0328
213 #define V3_STATID 0x032C
214 #define V4_STATID 0x0330
215 #define V5_STATID 0x0334
216 #define V6_STATID 0x0338
217 #define V7_STATID 0x033C
218
219 #define MAST_CTL 0x0400
220 #define MISC_CTL 0x0404
221 #define MISC_STAT 0x0408
222 #define USER_AM 0x040C
223 #define U2SPEC 0x04FC
224
225 #define VSI0_CTL 0x0F00
226 #define VSI0_BS 0x0F04
227 #define VSI0_BD 0x0F08
228 #define VSI0_TO 0x0F0C
229
230 #define VSI1_CTL 0x0F14
231 #define VSI1_BS 0x0F18
232 #define VSI1_BD 0x0F1C
233 #define VSI1_TO 0x0F20
234
235 #define VSI2_CTL 0x0F28
236 #define VSI2_BS 0x0F2C
237 #define VSI2_BD 0x0F30
238 #define VSI2_TO 0x0F34
239
240 #define VSI3_CTL 0x0F3C
241 #define VSI3_BS 0x0F40
242 #define VSI3_BD 0x0F44
243 #define VSI3_TO 0x0F48
244
245 #define VRAI_CTL 0x0F70
246 #define VRAI_BS 0x0F74
247 #define VCSR_CTL 0x0F80
248 #define VCSR_TO 0x0F84
249 #define V_AMERR 0x0F88
250 #define VAERR 0x0F8C
251
252 #define VSI4_CTL 0x0F90
253 #define VSI4_BS 0x0F94
254 #define VSI4_BD 0x0F98
255 #define VSI4_TO 0x0F9C
256
257 #define VSI5_CTL 0x0FA4
258 #define VSI5_BS 0x0FA8
259 #define VSI5_BD 0x0FAC
260 #define VSI5_TO 0x0FB0
261
262 #define VSI6_CTL 0x0FB8
263 #define VSI6_BS 0x0FBC
264 #define VSI6_BD 0x0FC0
265 #define VSI6_TO 0x0FC4
266
267 #define VSI7_CTL 0x0FCC
268 #define VSI7_BS 0x0FD0
269 #define VSI7_BD 0x0FD4
270 #define VSI7_TO 0x0FD8
271
272 #define VCSR_CLR 0x0FF4
273 #define VCSR_SET 0x0FF8
274 #define VCSR_BS 0x0FFC
275
276
277 // DMA General Control/Status Register DGCS (0x220)
278 // 32-24 || GO | STOPR | HALTR | 0 || CHAIN | 0 | 0 | 0 ||
279 // 23-16 || VON || VOFF ||
280 // 15-08 || ACT | STOP | HALT | 0 || DONE | LERR | VERR | P_ERR ||
281 // 07-00 || 0 | INT_S | INT_H | 0 || I_DNE | I_LER | I_VER | I_PER ||
282
283 // VON - Length Per DMA VMEBus Transfer
284 // 0000 = None
285 // 0001 = 256 Bytes
286 // 0010 = 512
287 // 0011 = 1024
288 // 0100 = 2048
289 // 0101 = 4096
290 // 0110 = 8192
291 // 0111 = 16384
292
293 // VOFF - wait between DMA tenures
294 // 0000 = 0 us
295 // 0001 = 16
296 // 0010 = 32
297 // 0011 = 64
298 // 0100 = 128
299 // 0101 = 256
300 // 0110 = 512
301 // 0111 = 1024
302
303 #endif

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