/[VMELinux]/driver/ca91c042.h
ViewVC logotype

Contents of /driver/ca91c042.h

Parent Directory Parent Directory | Revision Log Revision Log


Revision 1.4 - (show annotations)
Sat Oct 27 03:50:07 2001 UTC (17 years, 9 months ago) by jhuggins
Branch: MAIN
CVS Tags: vmelinux-1_3_0
Changes since 1.3: +50 -9 lines
File MIME type: text/plain
These changes add support for the extra images offered by the Universe II.
CVS : ----------------------------------------------------------------------
1 //------------------------------------------------------------------------------
2 //title: Tundra Universe PCI-VME Kernel Driver
3 //version: Linux 1.1
4 //date: March 1999
5 //designer: Michael Wyrick
6 //programmer: Michael Wyrick
7 //platform: Linux 2.4.x
8 //language: GCC 2.95 and 3.0
9 //module: ca91c042
10 //------------------------------------------------------------------------------
11 // Purpose: Provide a Kernel Driver to Linux for the Universe I and II
12 // Universe model number ca91c042
13 // Docs:
14 // This driver supports both the Universe and Universe II chips
15 //------------------------------------------------------------------------------
16 // RCS:
17 // $Id: ca91c042.h,v 1.4 2001/10/27 03:50:07 jhuggins Exp $
18 // $Log: ca91c042.h,v $
19 // Revision 1.4 2001/10/27 03:50:07 jhuggins
20 // These changes add support for the extra images offered by the Universe II.
21 // CVS : ----------------------------------------------------------------------
22 //
23 // Revision 1.4 2001/10/16 15:16:53 wyrick
24 // Minor Cleanup of Comments
25 //
26 //
27 //-----------------------------------------------------------------------------
28 #ifndef _ca91c042_H
29 #define _ca91c042_H
30
31 //-----------------------------------------------------------------------------
32 // Public Functions
33 //-----------------------------------------------------------------------------
34 // This is the typedef for a VmeIrqHandler
35 typedef void (*TirqHandler)(int vmeirq, int vector, void *dev_id, struct pt_regs *regs);
36 // This is the typedef for a DMA Transfer Callback function
37 typedef void (*TDMAcallback)(int status);
38
39 // Returns the PCI baseaddress of the Universe chip
40 char* Universe_BaseAddr(void);
41 // Returns the PCI IRQ That the universe is using
42 int Universe_IRQ(void);
43
44 char* mapvme(unsigned int pci, unsigned int vme, unsigned int size,
45 int image,int ctl);
46 void unmapvme(char *ptr, int image);
47
48 // Interrupt Stuff
49 void enable_vmeirq(unsigned int irq);
50 void disable_vmeirq(unsigned int irq);
51 int request_vmeirq(unsigned int irq, TirqHandler);
52 void free_vmeirq(unsigned int irq);
53
54 // DMA Stuff
55 void VME_DMA(void* pci, void* vme, unsigned int count, int ctl, TDMAcallback cback);
56 void VME_DMA_LinkedList(void* CmdPacketList,TDMAcallback cback);
57
58 // Misc
59 int VME_Bus_Error(void);
60
61 //-----------------------------------------------------------------------------
62 //
63 //-----------------------------------------------------------------------------
64 #define IRQ_VOWN 0x0001
65 #define IRQ_VIRQ1 0x0002
66 #define IRQ_VIRQ2 0x0004
67 #define IRQ_VIRQ3 0x0008
68 #define IRQ_VIRQ4 0x0010
69 #define IRQ_VIRQ5 0x0020
70 #define IRQ_VIRQ6 0x0040
71 #define IRQ_VIRQ7 0x0080
72 #define IRQ_DMA 0x0100
73 #define IRQ_LERR 0x0200
74 #define IRQ_VERR 0x0400
75 #define IRQ_res 0x0800
76 #define IRQ_IACK 0x1000
77 #define IRQ_SWINT 0x2000
78 #define IRQ_SYSFAIL 0x4000
79 #define IRQ_ACFAIL 0x8000
80
81 //-----------------------------------------------------------------------------
82 //
83 //-----------------------------------------------------------------------------
84 // See Page 2-77 in the Universe User Manual
85 typedef struct
86 {
87 unsigned int dctl; // DMA Control
88 unsigned int dtbc; // Transfer Byte Count
89 unsigned int dlv; // PCI Address
90 unsigned int res1; // Reserved
91 unsigned int dva; // Vme Address
92 unsigned int res2; // Reserved
93 unsigned int dcpp; // Pointer to Numed Cmd Packet with rPN
94 unsigned int res3; // Reserved
95 } TDMA_Cmd_Packet;
96
97 //-----------------------------------------------------------------------------
98 // Below here is normaly not used by a user module
99 //-----------------------------------------------------------------------------
100 #define DMATIMEOUT 2*HZ;
101
102 // Define for the Universe
103 #define SEEK_SET 0
104 #define SEEK_CUR 1
105
106 #define CONFIG_REG_SPACE 0xA0000000
107
108 #define PCI_SIZE_8 0x0001
109 #define PCI_SIZE_16 0x0002
110 #define PCI_SIZE_32 0x0003
111
112 #define IOCTL_SET_CTL 0xF001
113 #define IOCTL_SET_BS 0xF002
114 #define IOCTL_SET_BD 0xF003
115 #define IOCTL_SET_TO 0xF004
116 #define IOCTL_PCI_SIZE 0xF005
117 #define IOCTL_SET_MODE 0xF006
118 #define IOCTL_SET_WINT 0xF007 // Wait for interrupt before read
119
120 #define PCI_ID 0x0000
121 #define PCI_CSR 0x0004
122 #define PCI_CLASS 0x0008
123 #define PCI_MISC0 0x000C
124 #define PCI_BS 0x0010
125 #define PCI_MISC1 0x003C
126
127 #define LSI0_CTL 0x0100
128 #define LSI0_BS 0x0104
129 #define LSI0_BD 0x0108
130 #define LSI0_TO 0x010C
131
132 #define LSI1_CTL 0x0114
133 #define LSI1_BS 0x0118
134 #define LSI1_BD 0x011C
135 #define LSI1_TO 0x0120
136
137 #define LSI2_CTL 0x0128
138 #define LSI2_BS 0x012C
139 #define LSI2_BD 0x0130
140 #define LSI2_TO 0x0134
141
142 #define LSI3_CTL 0x013C
143 #define LSI3_BS 0x0140
144 #define LSI3_BD 0x0144
145 #define LSI3_TO 0x0148
146
147 #define LSI4_CTL 0x01A0
148 #define LSI4_BS 0x01A4
149 #define LSI4_BD 0x01A8
150 #define LSI4_TO 0x01AC
151
152 #define LSI5_CTL 0x01B4
153 #define LSI5_BS 0x01B8
154 #define LSI5_BD 0x01BC
155 #define LSI5_TO 0x01C0
156
157 #define LSI6_CTL 0x01C8
158 #define LSI6_BS 0x01CC
159 #define LSI6_BD 0x01D0
160 #define LSI6_TO 0x01D4
161
162 #define LSI7_CTL 0x01DC
163 #define LSI7_BS 0x01E0
164 #define LSI7_BD 0x01E4
165 #define LSI7_TO 0x01E8
166
167 #define SCYC_CTL 0x0170
168 #define SCYC_ADDR 0x0174
169 #define SCYC_EN 0x0178
170 #define SCYC_CMP 0x017C
171 #define SCYC_SWP 0x0180
172 #define LMISC 0x0184
173 #define SLSI 0x0188
174 #define L_CMDERR 0x018C
175 #define LAERR 0x0190
176
177 #define DCTL 0x0200
178 #define DTBC 0x0204
179 #define DLA 0x0208
180 #define DVA 0x0210
181 #define DCPP 0x0218
182 #define DGCS 0x0220
183 #define D_LLUE 0x0224
184
185 #define LINT_EN 0x0300
186 #define LINT_STAT 0x0304
187 #define LINT_MAP0 0x0308
188 #define LINT_MAP1 0x030C
189 #define VINT_EN 0x0310
190 #define VINT_STAT 0x0314
191 #define VINT_MAP0 0x0318
192 #define VINT_MAP1 0x031C
193 #define STATID 0x0320
194 #define V1_STATID 0x0324
195 #define V2_STATID 0x0328
196 #define V3_STATID 0x032C
197 #define V4_STATID 0x0330
198 #define V5_STATID 0x0334
199 #define V6_STATID 0x0338
200 #define V7_STATID 0x033C
201
202 #define MAST_CTL 0x0400
203 #define MISC_CTL 0x0404
204 #define MISC_STAT 0x0408
205 #define USER_AM 0x040C
206
207 #define VSI0_CTL 0x0F00
208 #define VSI0_BS 0x0F04
209 #define VSI0_BD 0x0F08
210 #define VSI0_TO 0x0F0C
211
212 #define VSI1_CTL 0x0F14
213 #define VSI1_BS 0x0F18
214 #define VSI1_BD 0x0F1C
215 #define VSI1_TO 0x0F20
216
217 #define VSI2_CTL 0x0F28
218 #define VSI2_BS 0x0F2C
219 #define VSI2_BD 0x0F30
220 #define VSI2_TO 0x0F34
221
222 #define VSI3_CTL 0x0F3C
223 #define VSI3_BS 0x0F40
224 #define VSI3_BD 0x0F44
225 #define VSI3_TO 0x0F48
226
227 #define VRAI_CTL 0x0F70
228 #define VRAI_BS 0x0F74
229 #define VCSR_CTL 0x0F80
230 #define VCSR_TO 0x0F84
231 #define V_AMERR 0x0F88
232 #define VAERR 0x0F8C
233
234 #define VSI4_CTL 0x0F90
235 #define VSI4_BS 0x0F94
236 #define VSI4_BD 0x0F98
237 #define VSI4_TO 0x0F9C
238
239 #define VSI5_CTL 0x0FA4
240 #define VSI5_BS 0x0FA8
241 #define VSI5_BD 0x0FAC
242 #define VSI5_TO 0x0FB0
243
244 #define VSI6_CTL 0x0FB8
245 #define VSI6_BS 0x0FBC
246 #define VSI6_BD 0x0FC0
247 #define VSI6_TO 0x0FC4
248
249 #define VSI7_CTL 0x0FCC
250 #define VSI7_BS 0x0FD0
251 #define VSI7_BD 0x0FD4
252 #define VSI7_TO 0x0FD8
253
254 #define VCSR_CLR 0x0FF4
255 #define VCSR_SET 0x0FF8
256 #define VCSR_BS 0x0FFC
257
258
259 // DMA General Control/Status Register DGCS (0x220)
260 // 32-24 || GO | STOPR | HALTR | 0 || CHAIN | 0 | 0 | 0 ||
261 // 23-16 || VON || VOFF ||
262 // 15-08 || ACT | STOP | HALT | 0 || DONE | LERR | VERR | P_ERR ||
263 // 07-00 || 0 | INT_S | INT_H | 0 || I_DNE | I_LER | I_VER | I_PER ||
264
265 // VON - Length Per DMA VMEBus Transfer
266 // 0000 = None
267 // 0001 = 256 Bytes
268 // 0010 = 512
269 // 0011 = 1024
270 // 0100 = 2048
271 // 0101 = 4096
272 // 0110 = 8192
273 // 0111 = 16384
274
275 // VOFF - wait between DMA tenures
276 // 0000 = 0 us
277 // 0001 = 16
278 // 0010 = 32
279 // 0011 = 64
280 // 0100 = 128
281 // 0101 = 256
282 // 0110 = 512
283 // 0111 = 1024
284
285 #endif

  ViewVC Help
Powered by ViewVC 1.2-dev