/[VMELinux]/driver/ca91c042.h
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Contents of /driver/ca91c042.h

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Revision 1.2 - (show annotations)
Mon Jun 18 14:57:36 2001 UTC (18 years, 1 month ago) by astro
Branch: MAIN
CVS Tags: vmelinux-1_1_2, Linux2_4_x
Changes since 1.1: +0 -16 lines
File MIME type: text/plain
Changed the device number from 70 to 221 as assigned by the Linux authorities.
1 //-----------------------------------------------------------------------------
2 // Copyright 1999, Transmitter Location Systems, LLC.
3 //-----------------------------------------------------------------------------
4 // Project : TLS-2000
5 // Title :
6 // Designer :
7 // Platform :
8 // Language :
9 //
10 //-----------------------------------------------------------------------------
11 // Purpose :
12 // Docs :
13 //-----------------------------------------------------------------------------
14 // RCS:
15 // $Id: ca91c042.h,v 1.2 2001/06/18 14:57:36 astro Exp $
16 //-----------------------------------------------------------------------------
17 #ifndef _ca91c042_H
18 #define _ca91c042_H
19
20 //-----------------------------------------------------------------------------
21 // Public Functions
22 //-----------------------------------------------------------------------------
23 // This is the typedef for a VmeIrqHandler
24 typedef void (*TirqHandler)(int vmeirq, int vector, void *dev_id, struct pt_regs *regs);
25 // This is the typedef for a DMA Transfer Callback function
26 typedef void (*TDMAcallback)(int status);
27
28 // Returns the PCI baseaddress of the Universe chip
29 char* Universe_BaseAddr(void);
30 // Returns the PCI IRQ That the universe is using
31 int Universe_IRQ(void);
32
33 char* mapvme(unsigned int pci, unsigned int vme, unsigned int size,
34 int image,int ctl);
35 void unmapvme(char *ptr, int image);
36
37 // Interrupt Stuff
38 void enable_vmeirq(unsigned int irq);
39 void disable_vmeirq(unsigned int irq);
40 int request_vmeirq(unsigned int irq, TirqHandler);
41 void free_vmeirq(unsigned int irq);
42
43 // DMA Stuff
44 void VME_DMA(void* pci, void* vme, unsigned int count, int ctl, TDMAcallback cback);
45 void VME_DMA_LinkedList(void* CmdPacketList,TDMAcallback cback);
46
47 //-----------------------------------------------------------------------------
48 //
49 //-----------------------------------------------------------------------------
50 #define IRQ_VOWN 0x0001
51 #define IRQ_VIRQ1 0x0002
52 #define IRQ_VIRQ2 0x0004
53 #define IRQ_VIRQ3 0x0008
54 #define IRQ_VIRQ4 0x0010
55 #define IRQ_VIRQ5 0x0020
56 #define IRQ_VIRQ6 0x0040
57 #define IRQ_VIRQ7 0x0080
58 #define IRQ_DMA 0x0100
59 #define IRQ_LERR 0x0200
60 #define IRQ_VERR 0x0400
61 #define IRQ_res 0x0800
62 #define IRQ_IACK 0x1000
63 #define IRQ_SWINT 0x2000
64 #define IRQ_SYSFAIL 0x4000
65 #define IRQ_ACFAIL 0x8000
66
67 //-----------------------------------------------------------------------------
68 //
69 //-----------------------------------------------------------------------------
70 // See Page 2-77 in the Universe User Manual
71 typedef struct {
72 unsigned int dctl; // DMA Control
73 unsigned int dtbc; // Transfer Byte Count
74 unsigned int dlv; // PCI Address
75 unsigned int res1; // Reserved
76 unsigned int dva; // Vme Address
77 unsigned int res2; // Reserved
78 unsigned int dcpp; // Pointer to Numed Cmd Packet with rPN
79 unsigned int res3; // Reserved
80 } TDMA_Cmd_Packet;
81
82 //-----------------------------------------------------------------------------
83 // Below here is normaly not used by a user module
84 //-----------------------------------------------------------------------------
85 #define DMATIMEOUT 2*HZ;
86
87 // Define for the Universe
88 #define SEEK_SET 0
89 #define SEEK_CUR 1
90
91 #define CONFIG_REG_SPACE 0xA0000000
92
93 #define PCI_SIZE_8 0x0001
94 #define PCI_SIZE_16 0x0002
95 #define PCI_SIZE_32 0x0003
96
97 #define IOCTL_SET_CTL 0xF001
98 #define IOCTL_SET_BS 0xF002
99 #define IOCTL_SET_BD 0xF003
100 #define IOCTL_SET_TO 0xF004
101 #define IOCTL_PCI_SIZE 0xF005
102 #define IOCTL_SET_MODE 0xF006
103 #define IOCTL_SET_WINT 0xF007 // Wait for interrupt before read
104
105 #define PCI_ID 0x0000
106 #define PCI_CSR 0x0004
107 #define PCI_CLASS 0x0008
108 #define PCI_MISC0 0x000C
109 #define PCI_BS 0x0010
110 #define PCI_MISC1 0x003C
111
112 #define LSI0_CTL 0x0100
113 #define LSI0_BS 0x0104
114 #define LSI0_BD 0x0108
115 #define LSI0_TO 0x010C
116
117 #define LSI1_CTL 0x0114
118 #define LSI1_BS 0x0118
119 #define LSI1_BD 0x011C
120 #define LSI1_TO 0x0120
121
122 #define LSI2_CTL 0x0128
123 #define LSI2_BS 0x012C
124 #define LSI2_BD 0x0130
125 #define LSI2_TO 0x0134
126
127 #define LSI3_CTL 0x013C
128 #define LSI3_BS 0x0140
129 #define LSI3_BD 0x0144
130 #define LSI3_TO 0x0148
131
132 #define SCYC_CTL 0x0170
133 #define SCYC_ADDR 0x0174
134 #define SCYC_EN 0x0178
135 #define SCYC_CMP 0x017C
136 #define SCYC_SWP 0x0180
137 #define LMISC 0x0184
138 #define SLSI 0x0188
139 #define L_CMDERR 0x018C
140 #define LAERR 0x0190
141
142 #define DCTL 0x0200
143 #define DTBC 0x0204
144 #define DLA 0x0208
145 #define DVA 0x0210
146 #define DCPP 0x0218
147 #define DGCS 0x0220
148 #define D_LLUE 0x0224
149
150 #define LINT_EN 0x0300
151 #define LINT_STAT 0x0304
152 #define LINT_MAP0 0x0308
153 #define LINT_MAP1 0x030C
154 #define VINT_EN 0x0310
155 #define VINT_STAT 0x0314
156 #define VINT_MAP0 0x0318
157 #define VINT_MAP1 0x031C
158 #define STATID 0x0320
159 #define V1_STATID 0x0324
160 #define V2_STATID 0x0328
161 #define V3_STATID 0x032C
162 #define V4_STATID 0x0330
163 #define V5_STATID 0x0334
164 #define V6_STATID 0x0338
165 #define V7_STATID 0x033C
166
167 #define MAST_CTL 0x0400
168 #define MISC_CTL 0x0404
169 #define MISC_STAT 0x0408
170 #define USER_AM 0x040C
171
172 #define VSI0_CTL 0x0F00
173 #define VSI0_BS 0x0F04
174 #define VSI0_BD 0x0F08
175 #define VSI0_TO 0x0F0C
176
177 #define VSI1_CTL 0x0F14
178 #define VSI1_BS 0x0F18
179 #define VSI1_BD 0x0F1C
180 #define VSI1_TO 0x0F20
181
182 #define VSI2_CTL 0x0F28
183 #define VSI2_BS 0x0F2C
184 #define VSI2_BD 0x0F30
185 #define VSI2_TO 0x0F34
186
187 #define VSI3_CTL 0x0F3C
188 #define VSI3_BS 0x0F40
189 #define VSI3_BD 0x0F44
190 #define VSI3_TO 0x0F48
191
192 #define VRAI_CTL 0x0F70
193 #define VRAI_BS 0x0F74
194 #define VCSR_CTL 0x0F80
195 #define VCSR_TO 0x0F84
196 #define V_AMERR 0x0F88
197 #define VAERR 0x0F8C
198
199 #define VCSR_CLR 0x0FF4
200 #define VCSR_SET 0x0FF8
201 #define VCSR_BS 0x0FFC
202
203
204 // DMA General Control/Status Register DGCS (0x220)
205 // 32-24 || GO | STOPR | HALTR | 0 || CHAIN | 0 | 0 | 0 ||
206 // 23-16 || VON || VOFF ||
207 // 15-08 || ACT | STOP | HALT | 0 || DONE | LERR | VERR | P_ERR ||
208 // 07-00 || 0 | INT_S | INT_H | 0 || I_DNE | I_LER | I_VER | I_PER ||
209
210 // VON - Length Per DMA VMEBus Transfer
211 // 0000 = None
212 // 0001 = 256 Bytes
213 // 0010 = 512
214 // 0011 = 1024
215 // 0100 = 2048
216 // 0101 = 4096
217 // 0110 = 8192
218 // 0111 = 16384
219
220 // VOFF - wait between DMA tenures
221 // 0000 = 0 us
222 // 0001 = 16
223 // 0010 = 32
224 // 0011 = 64
225 // 0100 = 128
226 // 0101 = 256
227 // 0110 = 512
228 // 0111 = 1024
229
230 #endif

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