/[VMELinux]/driver/ca91c042.h
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Contents of /driver/ca91c042.h

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Revision 1.3 - (show annotations)
Wed Oct 24 17:29:01 2001 UTC (17 years, 9 months ago) by jhuggins
Branch: MAIN
CVS Tags: vmelinux-1_2_0
Branch point for: vmelinux_1_2_0_patches
Changes since 1.2: +50 -40 lines
File MIME type: text/plain
Error occurred while calculating annotation data.
This version works with 2.4.x kernels with backward compatibility with 2.2.x.  This will not work with 2.0.x kernels.
CV: ----------------------------------------------------------------------
1 //------------------------------------------------------------------------------
2 //title: Tundra Universe PCI-VME Kernel Driver
3 //version: Linux 1.1
4 //date: March 1999
5 //designer: Michael Wyrick
6 //programmer: Michael Wyrick
7 //platform: Linux 2.4.x
8 //language: GCC 2.95 and 3.0
9 //module: ca91c042
10 //------------------------------------------------------------------------------
11 // Purpose: Provide a Kernel Driver to Linux for the Universe I and II
12 // Universe model number ca91c042
13 // Docs:
14 // This driver supports both the Universe and Universe II chips
15 //------------------------------------------------------------------------------
16 // RCS:
17 // $Id: ca91c042.h,v 1.3 2001/10/24 17:29:01 jhuggins Exp $
18 // $Log: ca91c042.h,v $
19 // Revision 1.3 2001/10/24 17:29:01 jhuggins
20 // This version works with 2.4.x kernels with backward compatibility with 2.2.x. This will not work with 2.0.x kernels.
21 // CV: ----------------------------------------------------------------------
22 //
23 // Revision 1.4 2001/10/16 15:16:53 wyrick
24 // Minor Cleanup of Comments
25 //
26 //
27 //-----------------------------------------------------------------------------
28 #ifndef _ca91c042_H
29 #define _ca91c042_H
30
31 //-----------------------------------------------------------------------------
32 // Public Functions
33 //-----------------------------------------------------------------------------
34 // This is the typedef for a VmeIrqHandler
35 typedef void (*TirqHandler)(int vmeirq, int vector, void *dev_id, struct pt_regs *regs);
36 // This is the typedef for a DMA Transfer Callback function
37 typedef void (*TDMAcallback)(int status);
38
39 // Returns the PCI baseaddress of the Universe chip
40 char* Universe_BaseAddr(void);
41 // Returns the PCI IRQ That the universe is using
42 int Universe_IRQ(void);
43
44 char* mapvme(unsigned int pci, unsigned int vme, unsigned int size,
45 int image,int ctl);
46 void unmapvme(char *ptr, int image);
47
48 // Interrupt Stuff
49 void enable_vmeirq(unsigned int irq);
50 void disable_vmeirq(unsigned int irq);
51 int request_vmeirq(unsigned int irq, TirqHandler);
52 void free_vmeirq(unsigned int irq);
53
54 // DMA Stuff
55 void VME_DMA(void* pci, void* vme, unsigned int count, int ctl, TDMAcallback cback);
56 void VME_DMA_LinkedList(void* CmdPacketList,TDMAcallback cback);
57
58 // Misc
59 int VME_Bus_Error(void);
60
61 //-----------------------------------------------------------------------------
62 //
63 //-----------------------------------------------------------------------------
64 #define IRQ_VOWN 0x0001
65 #define IRQ_VIRQ1 0x0002
66 #define IRQ_VIRQ2 0x0004
67 #define IRQ_VIRQ3 0x0008
68 #define IRQ_VIRQ4 0x0010
69 #define IRQ_VIRQ5 0x0020
70 #define IRQ_VIRQ6 0x0040
71 #define IRQ_VIRQ7 0x0080
72 #define IRQ_DMA 0x0100
73 #define IRQ_LERR 0x0200
74 #define IRQ_VERR 0x0400
75 #define IRQ_res 0x0800
76 #define IRQ_IACK 0x1000
77 #define IRQ_SWINT 0x2000
78 #define IRQ_SYSFAIL 0x4000
79 #define IRQ_ACFAIL 0x8000
80
81 //-----------------------------------------------------------------------------
82 //
83 //-----------------------------------------------------------------------------
84 // See Page 2-77 in the Universe User Manual
85 typedef struct {
86 unsigned int dctl; // DMA Control
87 unsigned int dtbc; // Transfer Byte Count
88 unsigned int dlv; // PCI Address
89 unsigned int res1; // Reserved
90 unsigned int dva; // Vme Address
91 unsigned int res2; // Reserved
92 unsigned int dcpp; // Pointer to Numed Cmd Packet with rPN
93 unsigned int res3; // Reserved
94 } TDMA_Cmd_Packet;
95
96 //-----------------------------------------------------------------------------
97 // Below here is normaly not used by a user module
98 //-----------------------------------------------------------------------------
99 #define DMATIMEOUT 2*HZ;
100
101 // Define for the Universe
102 #define SEEK_SET 0
103 #define SEEK_CUR 1
104
105 #define CONFIG_REG_SPACE 0xA0000000
106
107 #define PCI_SIZE_8 0x0001
108 #define PCI_SIZE_16 0x0002
109 #define PCI_SIZE_32 0x0003
110
111 #define IOCTL_SET_CTL 0xF001
112 #define IOCTL_SET_BS 0xF002
113 #define IOCTL_SET_BD 0xF003
114 #define IOCTL_SET_TO 0xF004
115 #define IOCTL_PCI_SIZE 0xF005
116 #define IOCTL_SET_MODE 0xF006
117 #define IOCTL_SET_WINT 0xF007 // Wait for interrupt before read
118
119 #define PCI_ID 0x0000
120 #define PCI_CSR 0x0004
121 #define PCI_CLASS 0x0008
122 #define PCI_MISC0 0x000C
123 #define PCI_BS 0x0010
124 #define PCI_MISC1 0x003C
125
126 #define LSI0_CTL 0x0100
127 #define LSI0_BS 0x0104
128 #define LSI0_BD 0x0108
129 #define LSI0_TO 0x010C
130
131 #define LSI1_CTL 0x0114
132 #define LSI1_BS 0x0118
133 #define LSI1_BD 0x011C
134 #define LSI1_TO 0x0120
135
136 #define LSI2_CTL 0x0128
137 #define LSI2_BS 0x012C
138 #define LSI2_BD 0x0130
139 #define LSI2_TO 0x0134
140
141 #define LSI3_CTL 0x013C
142 #define LSI3_BS 0x0140
143 #define LSI3_BD 0x0144
144 #define LSI3_TO 0x0148
145
146 #define SCYC_CTL 0x0170
147 #define SCYC_ADDR 0x0174
148 #define SCYC_EN 0x0178
149 #define SCYC_CMP 0x017C
150 #define SCYC_SWP 0x0180
151 #define LMISC 0x0184
152 #define SLSI 0x0188
153 #define L_CMDERR 0x018C
154 #define LAERR 0x0190
155
156 #define DCTL 0x0200
157 #define DTBC 0x0204
158 #define DLA 0x0208
159 #define DVA 0x0210
160 #define DCPP 0x0218
161 #define DGCS 0x0220
162 #define D_LLUE 0x0224
163
164 #define LINT_EN 0x0300
165 #define LINT_STAT 0x0304
166 #define LINT_MAP0 0x0308
167 #define LINT_MAP1 0x030C
168 #define VINT_EN 0x0310
169 #define VINT_STAT 0x0314
170 #define VINT_MAP0 0x0318
171 #define VINT_MAP1 0x031C
172 #define STATID 0x0320
173 #define V1_STATID 0x0324
174 #define V2_STATID 0x0328
175 #define V3_STATID 0x032C
176 #define V4_STATID 0x0330
177 #define V5_STATID 0x0334
178 #define V6_STATID 0x0338
179 #define V7_STATID 0x033C
180
181 #define MAST_CTL 0x0400
182 #define MISC_CTL 0x0404
183 #define MISC_STAT 0x0408
184 #define USER_AM 0x040C
185
186 #define VSI0_CTL 0x0F00
187 #define VSI0_BS 0x0F04
188 #define VSI0_BD 0x0F08
189 #define VSI0_TO 0x0F0C
190
191 #define VSI1_CTL 0x0F14
192 #define VSI1_BS 0x0F18
193 #define VSI1_BD 0x0F1C
194 #define VSI1_TO 0x0F20
195
196 #define VSI2_CTL 0x0F28
197 #define VSI2_BS 0x0F2C
198 #define VSI2_BD 0x0F30
199 #define VSI2_TO 0x0F34
200
201 #define VSI3_CTL 0x0F3C
202 #define VSI3_BS 0x0F40
203 #define VSI3_BD 0x0F44
204 #define VSI3_TO 0x0F48
205
206 #define VRAI_CTL 0x0F70
207 #define VRAI_BS 0x0F74
208 #define VCSR_CTL 0x0F80
209 #define VCSR_TO 0x0F84
210 #define V_AMERR 0x0F88
211 #define VAERR 0x0F8C
212
213 #define VCSR_CLR 0x0FF4
214 #define VCSR_SET 0x0FF8
215 #define VCSR_BS 0x0FFC
216
217
218 // DMA General Control/Status Register DGCS (0x220)
219 // 32-24 || GO | STOPR | HALTR | 0 || CHAIN | 0 | 0 | 0 ||
220 // 23-16 || VON || VOFF ||
221 // 15-08 || ACT | STOP | HALT | 0 || DONE | LERR | VERR | P_ERR ||
222 // 07-00 || 0 | INT_S | INT_H | 0 || I_DNE | I_LER | I_VER | I_PER ||
223
224 // VON - Length Per DMA VMEBus Transfer
225 // 0000 = None
226 // 0001 = 256 Bytes
227 // 0010 = 512
228 // 0011 = 1024
229 // 0100 = 2048
230 // 0101 = 4096
231 // 0110 = 8192
232 // 0111 = 16384
233
234 // VOFF - wait between DMA tenures
235 // 0000 = 0 us
236 // 0001 = 16
237 // 0010 = 32
238 // 0011 = 64
239 // 0100 = 128
240 // 0101 = 256
241 // 0110 = 512
242 // 0111 = 1024
243
244 #endif

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