/[VMELinux]/driver/ca91c042.c
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*** ca91c042.c	2001/06/28 21:14:22	1.3
--- ca91c042.c	2001/10/24 17:29:01	1.4
***************
*** 1,11 ****
  //------------------------------------------------------------------------------  
  //title: Tundra Universe PCI-VME Kernel Driver
! //version: Linux 
  //date: March 1999                                                                
  //designer: Michael Wyrick                                                      
  //programmer: Michael Wyrick                                                    
! //platform: Linux 2.2.12
! //language: GCC 2.8.1
  //module: ca91c042
  //------------------------------------------------------------------------------  
  //  Purpose: Provide a Kernel Driver to Linux for the Universe I and II 
--- 1,11 ----
  //------------------------------------------------------------------------------  
  //title: Tundra Universe PCI-VME Kernel Driver
! //version: Linux 1.1
  //date: March 1999                                                                
  //designer: Michael Wyrick                                                      
  //programmer: Michael Wyrick                                                    
! //platform: Linux 2.4.x
! //language: GCC 2.95 and 3.0
  //module: ca91c042
  //------------------------------------------------------------------------------  
  //  Purpose: Provide a Kernel Driver to Linux for the Universe I and II 
***************
*** 14,32 ****
  //    This driver supports both the Universe and Universe II chips                                     
  //------------------------------------------------------------------------------  
  // RCS:
! // $Id: ca91c042.c,v 1.3 2001/06/28 21:14:22 wyrick Exp $
  //
  //-----------------------------------------------------------------------------
  #define MODULE
  
! static char Version[] = "1.1 01Jun28";
  
  #include <linux/config.h>
  #include <linux/version.h>
  
  #ifdef CONFIG_MODVERSIONS
! #define MODVERSIONS
! #include <linux/modversions.h>
  #endif
  
  #include <linux/module.h>
--- 14,40 ----
  //    This driver supports both the Universe and Universe II chips                                     
  //------------------------------------------------------------------------------  
  // RCS:
! // $Id: ca91c042.c,v 1.4 2001/10/24 17:29:01 jhuggins Exp $
! // $Log: ca91c042.c,v $
! // Revision 1.4  2001/10/24 17:29:01  jhuggins
! // This version works with 2.4.x kernels with backward compatibility with 2.2.x.  This will not work with 2.0.x kernels.
! // CV: ----------------------------------------------------------------------
! //
! // Revision 1.6  2001/10/16 15:16:53  wyrick
! // Minor Cleanup of Comments
! //
  //
  //-----------------------------------------------------------------------------
  #define MODULE
  
! static char Version[] = "1.1 2001Oct16";
  
  #include <linux/config.h>
  #include <linux/version.h>
  
  #ifdef CONFIG_MODVERSIONS
!   #define MODVERSIONS
!   #include <linux/modversions.h>
  #endif
  
  #include <linux/module.h>
***************
*** 40,51 ****
  
  #include "ca91c042.h"
  
- #if LINUX_VERSION_CODE < 0x020100
- #define	ioremap	vremap
- #define	iounmap	vfree
- #endif
- 
- 
  //----------------------------------------------------------------------------
  // Prototypes
  //----------------------------------------------------------------------------
--- 48,53 ----
***************
*** 67,79 ****
  
  static struct file_operations uni_fops = 
  {
!   llseek: uni_llseek,
!   read: uni_read,
!   write: uni_write,
!   poll: uni_poll,     // uni_poll   
!   ioctl: uni_ioctl,
!   open: uni_open,
!   release: uni_release, 
  };
  
  static int aCTL[] = {LSI0_CTL, LSI1_CTL, LSI2_CTL, LSI3_CTL};
--- 69,81 ----
  
  static struct file_operations uni_fops = 
  {
!   llseek:   uni_llseek,
!   read:     uni_read,
!   write:    uni_write,
!   poll:     uni_poll,     // uni_poll   
!   ioctl:    uni_ioctl,
!   open:     uni_open,
!   release:  uni_release 
  };
  
  static int aCTL[] = {LSI0_CTL, LSI1_CTL, LSI2_CTL, LSI3_CTL};
***************
*** 84,90 ****
  //----------------------------------------------------------------------------
  // Vars and Defines
  //----------------------------------------------------------------------------
! #define UNI_MAJOR   	  221
  #define MAX_MINOR 	    8
  #define CONTROL_MINOR   8
  
--- 86,92 ----
  //----------------------------------------------------------------------------
  // Vars and Defines
  //----------------------------------------------------------------------------
! #define UNI_MAJOR     221
  #define MAX_MINOR 	    8
  #define CONTROL_MINOR   8
  
***************
*** 98,104 ****
  static int OkToWrite[MAX_MINOR + 1];        // Can I write to the Hardware
  
  static int opened[MAX_MINOR + 1];
! static int mode[MAX_MINOR + 1];               // DMA or Programmed I/O
  
  static unsigned long DMA[MAX_MINOR + 1];    // DMA Control Reg
  
--- 100,106 ----
  static int OkToWrite[MAX_MINOR + 1];        // Can I write to the Hardware
  
  static int opened[MAX_MINOR + 1];
! static int mode[MAX_MINOR + 1];             // DMA or Programmed I/O
  
  static unsigned long DMA[MAX_MINOR + 1];    // DMA Control Reg
  
***************
*** 114,122 ****
  // Hold the VME Irq Handlers
  static TirqHandler vmeirqs[7] = {NULL,NULL,NULL,NULL,NULL,NULL,NULL};
  static short vmeirqbit[7]     = {IRQ_VIRQ1, IRQ_VIRQ2, IRQ_VIRQ3, IRQ_VIRQ4,
!   IRQ_VIRQ5, IRQ_VIRQ6, IRQ_VIRQ7};               
  static int vmevec[7]          = {V1_STATID, V2_STATID, V3_STATID, V4_STATID,
!   V5_STATID, V6_STATID, V7_STATID};
  
  // Status Vars
  static unsigned int reads  = 0;
--- 116,124 ----
  // Hold the VME Irq Handlers
  static TirqHandler vmeirqs[7] = {NULL,NULL,NULL,NULL,NULL,NULL,NULL};
  static short vmeirqbit[7]     = {IRQ_VIRQ1, IRQ_VIRQ2, IRQ_VIRQ3, IRQ_VIRQ4,
!                                  IRQ_VIRQ5, IRQ_VIRQ6, IRQ_VIRQ7};               
  static int vmevec[7]          = {V1_STATID, V2_STATID, V3_STATID, V4_STATID,
!                                  V5_STATID, V6_STATID, V7_STATID};
  
  // Status Vars
  static unsigned int reads  = 0;
***************
*** 142,150 ****
  
    p += sprintf(p,"  baseaddr = %08X\n",(int)baseaddr);
    p += sprintf(p,"  Stats  reads = %i  writes = %i  ioctls = %i\n",
!                reads,writes,ioctls);
  
!   for(x=0;x<4;x+=2) {
      temp1 = readl(baseaddr+aCTL[x]);
      temp2 = readl(baseaddr+aCTL[x+1]);
      p += sprintf(p,"  LSI%i_CTL = %08X    LSI%i_CTL = %08X\n",x,temp1,x+1,temp2);
--- 144,152 ----
  
    p += sprintf(p,"  baseaddr = %08X\n",(int)baseaddr);
    p += sprintf(p,"  Stats  reads = %i  writes = %i  ioctls = %i\n",
!                  reads,writes,ioctls);
  
!   for (x=0;x<4;x+=2) {
      temp1 = readl(baseaddr+aCTL[x]);
      temp2 = readl(baseaddr+aCTL[x+1]);
      p += sprintf(p,"  LSI%i_CTL = %08X    LSI%i_CTL = %08X\n",x,temp1,x+1,temp2);
***************
*** 159,176 ****
      p += sprintf(p,"  LSI%i_TO  = %08X    LSI%i_TO  = %08X\n",x,temp1,x+1,temp2);
    }  
  
!   for(x=0;x<3;x+=2)
      p += sprintf(p,"  image_va%i   = %08X     image_va%i   = %08X\n",
                   x,image_va[x],x+1,image_va[x+1]); 
    p += sprintf(p,"\nDriver Program Status:\n");  
  
!   for(x=0;x<3;x+=2)
      p += sprintf(p,"  DMACTL %i    = %08lX DMACTL %i    = %08lX\n",
                   x,DMA[x],x+1,DMA[x+1]);        
!   for(x=0;x<3;x+=2)
      p += sprintf(p,"  OkToWrite %i = %1X        OkToWrite %i = %1X\n",
                   x,OkToWrite[x],x+1,OkToWrite[x+1]); 
!   for(x=0;x<3;x+=2)
      p += sprintf(p,"  Mode %i      = %1X        Mode %i      = %1X\n",
                   x,mode[x],x+1,mode[x+1]); 
  
--- 161,178 ----
      p += sprintf(p,"  LSI%i_TO  = %08X    LSI%i_TO  = %08X\n",x,temp1,x+1,temp2);
    }  
  
!   for (x=0;x<3;x+=2)
      p += sprintf(p,"  image_va%i   = %08X     image_va%i   = %08X\n",
                   x,image_va[x],x+1,image_va[x+1]); 
    p += sprintf(p,"\nDriver Program Status:\n");  
  
!   for (x=0;x<3;x+=2)
      p += sprintf(p,"  DMACTL %i    = %08lX DMACTL %i    = %08lX\n",
                   x,DMA[x],x+1,DMA[x+1]);        
!   for (x=0;x<3;x+=2)
      p += sprintf(p,"  OkToWrite %i = %1X        OkToWrite %i = %1X\n",
                   x,OkToWrite[x],x+1,OkToWrite[x+1]); 
!   for (x=0;x<3;x+=2)
      p += sprintf(p,"  Mode %i      = %1X        Mode %i      = %1X\n",
                   x,mode[x],x+1,mode[x+1]); 
  
***************
*** 178,190 ****
  
    temp1 = 0;
    p += sprintf(p, "VMEIrqs Assigned: ");
!   for(x=0;x<7;x++) {
!     if(vmeirqs[x] != NULL) {
        p += sprintf(p, "%i ",x+1);
        temp1++;
      }
    }
!   if(temp1 == 0)
      p += sprintf(p, "none\n");
    else
      p += sprintf(p,"\n");  
--- 180,192 ----
  
    temp1 = 0;
    p += sprintf(p, "VMEIrqs Assigned: ");
!   for (x=0;x<7;x++) {
!     if (vmeirqs[x] != NULL) {
        p += sprintf(p, "%i ",x+1);
        temp1++;
      }
    }
!   if (temp1 == 0)
      p += sprintf(p, "none\n");
    else
      p += sprintf(p,"\n");  
***************
*** 229,244 ****
  {
    unsigned int minor = MINOR(inode->i_rdev);
  
!   if(minor > MAX_MINOR) {
      return(-ENODEV);
    }
  
!   if(minor == CONTROL_MINOR) {
      opened[minor]++;
      return(0);
    }
  
!   if(!opened[minor]) {
      opened[minor] = 1;
      return(0);
    } else
--- 231,246 ----
  {
    unsigned int minor = MINOR(inode->i_rdev);
  
!   if (minor > MAX_MINOR) {
      return(-ENODEV);
    }
  
!   if (minor == CONTROL_MINOR) {
      opened[minor]++;
      return(0);
    }
  
!   if (!opened[minor]) {
      opened[minor] = 1;
      return(0);
    } else
***************
*** 269,276 ****
    unsigned int minor = MINOR(file->f_dentry->d_inode->i_rdev);
    unsigned int toffset,base,paddr;
  
!   if(whence == SEEK_SET) {
!     if(minor == CONTROL_MINOR) {
        image_ptr[minor] = offset;
      } else {
        toffset = readl(baseaddr+aTO[minor]);    
--- 271,278 ----
    unsigned int minor = MINOR(file->f_dentry->d_inode->i_rdev);
    unsigned int toffset,base,paddr;
  
!   if (whence == SEEK_SET) {
!     if (minor == CONTROL_MINOR) {
        image_ptr[minor] = offset;
      } else {
        toffset = readl(baseaddr+aTO[minor]);    
***************
*** 279,285 ****
        image_ptr[minor] = (int)(image_ba[minor]+(paddr-base));
      }  
      return 0;
!   } else if(whence == SEEK_CUR) {
      image_ptr[minor] += offset;
      return 0;
    } else
--- 281,287 ----
        image_ptr[minor] = (int)(image_ba[minor]+(paddr-base));
      }  
      return 0;
!   } else if (whence == SEEK_CUR) {
      image_ptr[minor] += offset;
      return 0;
    } else
***************
*** 305,339 ****
  
    char *DMA_Buffer;
    unsigned int DMA_Buffer_Size = 0, 
!   order = 0,
!   a_size = 0,
!   dma_align = 0,
!   timeout = 0;                     
!   int val,
!   pci = 0,
!   vme = 0,
!   okcount = 0;
  
!   if(minor == CONTROL_MINOR) {
      p = (int)image_ptr[minor];
      v = readl(baseaddr+p);    
      __copy_to_user(temp,&v,4);
    } else {
      reads++;                
!     if(OkToWrite[minor]) {
!       if(mode[minor] == MODE_PROGRAMMED) {
          numt = count;
          remain = count;
  
          // Calc the number of longs we need
          numt = count / 4;
          remain = count % 4;
!         for(x=0;x<numt;x++) {
            vl = readl(image_ptr[minor]);    
  
            // Lets Check for a Bus Error
            tmp = readl(baseaddr+PCI_CSR);
!           if(tmp & 0x08000000) {
              writel(tmp,baseaddr+PCI_CSR);
              return(okcount);
            } else
--- 307,341 ----
  
    char *DMA_Buffer;
    unsigned int DMA_Buffer_Size = 0, 
!     order     = 0,
!     a_size    = 0,
!     dma_align = 0,
!     timeout   = 0;                     
!   int val     = 0,
!     pci       = 0,
!     vme       = 0,
!     okcount   = 0;
  
!   if (minor == CONTROL_MINOR) {
      p = (int)image_ptr[minor];
      v = readl(baseaddr+p);    
      __copy_to_user(temp,&v,4);
    } else {
      reads++;                
!     if (OkToWrite[minor]) {
!       if (mode[minor] == MODE_PROGRAMMED) {
          numt = count;
          remain = count;
  
          // Calc the number of longs we need
          numt = count / 4;
          remain = count % 4;
!         for (x=0;x<numt;x++) {
            vl = readl(image_ptr[minor]);    
  
            // Lets Check for a Bus Error
            tmp = readl(baseaddr+PCI_CSR);
!           if (tmp & 0x08000000) {
              writel(tmp,baseaddr+PCI_CSR);
              return(okcount);
            } else
***************
*** 347,358 ****
          // Calc the number of Words we need
          numt = remain / 2;
          remain = remain % 2;
!         for(x=0;x<numt;x++) {
            vs = readw(image_ptr[minor]);    
  
            // Lets Check for a Bus Error
            tmp = readl(baseaddr+PCI_CSR);
!           if(tmp & 0x08000000) {
              writel(tmp,baseaddr+PCI_CSR);
              return(okcount);
            } else
--- 349,360 ----
          // Calc the number of Words we need
          numt = remain / 2;
          remain = remain % 2;
!         for (x=0;x<numt;x++) {
            vs = readw(image_ptr[minor]);    
  
            // Lets Check for a Bus Error
            tmp = readl(baseaddr+PCI_CSR);
!           if (tmp & 0x08000000) {
              writel(tmp,baseaddr+PCI_CSR);
              return(okcount);
            } else
***************
*** 363,374 ****
            temp+=2;
          }  
  
!         for(x=0;x<remain;x++) {
            vc = readb(image_ptr[minor]);    
  
            // Lets Check for a Bus Error
            tmp = readl(baseaddr+PCI_CSR);
!           if(tmp & 0x08000000) {
              writel(tmp,baseaddr+PCI_CSR);
              return(okcount);
            } else
--- 365,376 ----
            temp+=2;
          }  
  
!         for (x=0;x<remain;x++) {
            vc = readb(image_ptr[minor]);    
  
            // Lets Check for a Bus Error
            tmp = readl(baseaddr+PCI_CSR);
!           if (tmp & 0x08000000) {
              writel(tmp,baseaddr+PCI_CSR);
              return(okcount);
            } else
***************
*** 379,391 ****
            temp+=1;
          }  
  
!       } else if(mode[minor] == MODE_DMA) {
          // ------------------------------------------------------------------
          //
          // ------------------------------------------------------------------      
          // Wait for DMA to finish, This needs to be changed
          val = readl(baseaddr+DGCS);
!         while((val & 0x00008000) && (timeout++ < 1000000))
            val = readl(baseaddr+DGCS);
  
          // VME Address						      
--- 381,393 ----
            temp+=1;
          }  
  
!       } else if (mode[minor] == MODE_DMA) {
          // ------------------------------------------------------------------
          //
          // ------------------------------------------------------------------      
          // Wait for DMA to finish, This needs to be changed
          val = readl(baseaddr+DGCS);
!         while ((val & 0x00008000) && (timeout++ < 1000000))
            val = readl(baseaddr+DGCS);
  
          // VME Address						      
***************
*** 395,401 ****
          // Setup DMA Buffer to read data into
          DMA_Buffer_Size = count + ((int)image_ptr % 8) + dma_align;         
          a_size = PAGE_SIZE;
!         while(a_size < DMA_Buffer_Size) {
            order++;
            a_size <<= 1;
          }
--- 397,403 ----
          // Setup DMA Buffer to read data into
          DMA_Buffer_Size = count + ((int)image_ptr % 8) + dma_align;         
          a_size = PAGE_SIZE;
!         while (a_size < DMA_Buffer_Size) {
            order++;
            a_size <<= 1;
          }
***************
*** 406,427 ****
  
          // Setup DMA regs
          writel(DMA[minor],baseaddr+DCTL);       // Setup Control Reg
!         writel(count,baseaddr+DTBC);                // Count	    
!         writel(pci,baseaddr+DLA);           // PCI Address
!         writel(vme,baseaddr+DVA);           // VME Address
  
          // Start DMA
          writel(0x80006F00,baseaddr+DGCS);       // GO
  
          // Wait for DMA to finish, This needs to be changed
          val = readl(baseaddr+DGCS);
!         while((val & 0x00008000) && (timeout++ < 100000))
            val = readl(baseaddr+DGCS);
  
!         if(timeout == 100000)
            printk("<<ca91c042 DMA Timed out>>\n");
  
!         if(! (val & 0x00000800)) {  // An Error Happened
            count -= readl(baseaddr+DTBC);    
          }
  
--- 408,429 ----
  
          // Setup DMA regs
          writel(DMA[minor],baseaddr+DCTL);       // Setup Control Reg
!         writel(count,baseaddr+DTBC);            // Count	    
!         writel(pci,baseaddr+DLA);               // PCI Address
!         writel(vme,baseaddr+DVA);               // VME Address
  
          // Start DMA
          writel(0x80006F00,baseaddr+DGCS);       // GO
  
          // Wait for DMA to finish, This needs to be changed
          val = readl(baseaddr+DGCS);
!         while ((val & 0x00008000) && (timeout++ < 100000))
            val = readl(baseaddr+DGCS);
  
!         if (timeout == 100000)
            printk("<<ca91c042 DMA Timed out>>\n");
  
!         if (! (val & 0x00000800)) {  // An Error Happened
            count -= readl(baseaddr+DTBC);    
          }
  
***************
*** 456,491 ****
  
    char *DMA_Buffer;
    unsigned int DMA_Buffer_Size = 0, 
!   order = 0,
!   a_size = 0,
!   dma_align = 0,
!   timeout = 0;                     
    int val,
!   pci = 0,
!   vme = 0,
!   okcount = 0;
  
    writes++;
!   if(minor == CONTROL_MINOR) {
      __copy_from_user(&vl,temp,4);
      p = (int)image_ptr[minor];
      writel(vl,baseaddr+p);
    } else {
!     if(OkToWrite[minor]) {
!       if(mode[minor] == MODE_PROGRAMMED) {
          // Calc the number of longs we need
          numt = count;
          remain = count;
  
          numt = count / 4;
          remain = count % 4;
!         for(x=0;x<numt;x++) {
            __copy_from_user(&vl,temp,4);
            writel(vl,image_ptr[minor]);
  
            // Lets Check for a Bus Error
            tmp = readl(baseaddr+PCI_CSR);
!           if(tmp & 0x08000000) {
              writel(tmp,baseaddr+PCI_CSR);
              return(okcount);
            } else
--- 458,493 ----
  
    char *DMA_Buffer;
    unsigned int DMA_Buffer_Size = 0, 
!     order     = 0,
!     a_size    = 0,
!     dma_align = 0,
!     timeout   = 0;                     
    int val,
!     pci       = 0,
!     vme       = 0,
!     okcount   = 0;
  
    writes++;
!   if (minor == CONTROL_MINOR) {
      __copy_from_user(&vl,temp,4);
      p = (int)image_ptr[minor];
      writel(vl,baseaddr+p);
    } else {
!     if (OkToWrite[minor]) {
!       if (mode[minor] == MODE_PROGRAMMED) {
          // Calc the number of longs we need
          numt = count;
          remain = count;
  
          numt = count / 4;
          remain = count % 4;
!         for (x=0;x<numt;x++) {
            __copy_from_user(&vl,temp,4);
            writel(vl,image_ptr[minor]);
  
            // Lets Check for a Bus Error
            tmp = readl(baseaddr+PCI_CSR);
!           if (tmp & 0x08000000) {
              writel(tmp,baseaddr+PCI_CSR);
              return(okcount);
            } else
***************
*** 499,511 ****
          numt = remain / 2;
          remain = remain % 2;
  
!         for(x=0;x<numt;x++) {
            __copy_from_user(&vs,temp,2);
            writew(vs,image_ptr[minor]);
  
            // Lets Check for a Bus Error
            tmp = readl(baseaddr+PCI_CSR);
!           if(tmp & 0x08000000) {
              writel(tmp,baseaddr+PCI_CSR);
              return(okcount);
            } else
--- 501,513 ----
          numt = remain / 2;
          remain = remain % 2;
  
!         for (x=0;x<numt;x++) {
            __copy_from_user(&vs,temp,2);
            writew(vs,image_ptr[minor]);
  
            // Lets Check for a Bus Error
            tmp = readl(baseaddr+PCI_CSR);
!           if (tmp & 0x08000000) {
              writel(tmp,baseaddr+PCI_CSR);
              return(okcount);
            } else
***************
*** 515,527 ****
            temp+=2;
          }  
  
!         for(x=0;x<remain;x++) {
            __copy_from_user(&vc,temp,1);
            writeb(vc,image_ptr[minor]);
  
            // Lets Check for a Bus Error
            tmp = readl(baseaddr+PCI_CSR);
!           if(tmp & 0x08000000) {
              writel(tmp,baseaddr+PCI_CSR);
              return(okcount);
            } else
--- 517,529 ----
            temp+=2;
          }  
  
!         for (x=0;x<remain;x++) {
            __copy_from_user(&vc,temp,1);
            writeb(vc,image_ptr[minor]);
  
            // Lets Check for a Bus Error
            tmp = readl(baseaddr+PCI_CSR);
!           if (tmp & 0x08000000) {
              writel(tmp,baseaddr+PCI_CSR);
              return(okcount);
            } else
***************
*** 533,550 ****
  
          // Lets Check for a Bus Error
          tmp = readl(baseaddr+PCI_CSR);
!         if(tmp & 0x08000000) {  // S_TA is Set
            writel(0x08000000,baseaddr+PCI_CSR);
            count = 0;
          }
  
!       } else if(mode[minor] == MODE_DMA) {
          // ------------------------------------------------------------------
          //
          // ------------------------------------------------------------------      
          // Wait for DMA to finish, This needs to be changed
          val = readl(baseaddr+DGCS);
!         while((val & 0x00008000) && (timeout++ < 100000))
            val = readl(baseaddr+DGCS);
  
          // Setup DMA Buffer to write data into
--- 535,552 ----
  
          // Lets Check for a Bus Error
          tmp = readl(baseaddr+PCI_CSR);
!         if (tmp & 0x08000000) {  // S_TA is Set
            writel(0x08000000,baseaddr+PCI_CSR);
            count = 0;
          }
  
!       } else if (mode[minor] == MODE_DMA) {
          // ------------------------------------------------------------------
          //
          // ------------------------------------------------------------------      
          // Wait for DMA to finish, This needs to be changed
          val = readl(baseaddr+DGCS);
!         while ((val & 0x00008000) && (timeout++ < 100000))
            val = readl(baseaddr+DGCS);
  
          // Setup DMA Buffer to write data into
***************
*** 554,560 ****
  
          DMA_Buffer_Size = count + ((int)image_ptr % 8) + dma_align;         
          a_size = PAGE_SIZE;
!         while(a_size < DMA_Buffer_Size) {
            order++;
            a_size <<= 1;
          }
--- 556,562 ----
  
          DMA_Buffer_Size = count + ((int)image_ptr % 8) + dma_align;         
          a_size = PAGE_SIZE;
!         while (a_size < DMA_Buffer_Size) {
            order++;
            a_size <<= 1;
          }
***************
*** 563,590 ****
          // Copy User Memory into buffer
          __copy_from_user(DMA_Buffer + dma_align,temp,count);
  
- 
          // PCI Address
          pci = virt_to_bus(DMA_Buffer) + dma_align;
  
          // Setup DMA regs
!         writel(DMA[minor]|0x80000000,baseaddr+DCTL);    // Setup Control Reg
!         writel(count,baseaddr+DTBC);                // Count	    
!         writel(pci,baseaddr+DLA);           // PCI Address
!         writel(vme,baseaddr+DVA);           // VME Address
  
          // Start DMA
!         writel(0x80006F00,baseaddr+DGCS);       // GO
  
          // Wait for DMA to finish, This needs to be changed
          val = readl(baseaddr+DGCS);
!         while((val & 0x00008000) && (timeout++ < 100000))
            val = readl(baseaddr+DGCS);
  
!         if(timeout == 100000)
            printk("<<ca91c042 DMA Timed out>>\n");
  
!         if(! (val & 0x00000800)) {  // An Error Happened
            // The Universe Seems to return an invalid value in DTBC on
            // Bus Errors during DMA, so invalidate the count
            count = 0;
--- 565,591 ----
          // Copy User Memory into buffer
          __copy_from_user(DMA_Buffer + dma_align,temp,count);
  
          // PCI Address
          pci = virt_to_bus(DMA_Buffer) + dma_align;
  
          // Setup DMA regs
!         writel(DMA[minor]|0x80000000,baseaddr+DCTL);  // Setup Control Reg
!         writel(count,baseaddr+DTBC);                  // Count	    
!         writel(pci,baseaddr+DLA);                     // PCI Address
!         writel(vme,baseaddr+DVA);                     // VME Address
  
          // Start DMA
!         writel(0x80006F00,baseaddr+DGCS);             // GO
  
          // Wait for DMA to finish, This needs to be changed
          val = readl(baseaddr+DGCS);
!         while ((val & 0x00008000) && (timeout++ < 100000))
            val = readl(baseaddr+DGCS);
  
!         if (timeout == 100000)
            printk("<<ca91c042 DMA Timed out>>\n");
  
!         if (! (val & 0x00000800)) {  // An Error Happened
            // The Universe Seems to return an invalid value in DTBC on
            // Bus Errors during DMA, so invalidate the count
            count = 0;
***************
*** 608,669 ****
    unsigned int sizetomap = 0, to = 0, bs = 0;
  
    ioctls++;
!   switch(cmd) {
!     case IOCTL_SET_CTL:
!       writel(arg,baseaddr+aCTL[minor]);
! 
!       // Lets compute and save the DMA CTL Register
!       DMA[minor] = arg & 0x00FFFF00;
!       break;
! 
!     case IOCTL_SET_MODE:
!       mode[minor] = arg;
!       break;        
! 
!       // Lets Map the VME Bus to the PCI Bus
!       //
!       // << NOTE >> BD Must already be set before you call this!!!!
!       //
!       //
!     case IOCTL_SET_BS:
!       writel(arg,baseaddr+aBS[minor]);
!       if(image_ba[minor])
!         iounmap(image_ba[minor]);
! 
!       // This uses the BD Register to Find the size of the Image Mapping		
!       sizetomap = readl(baseaddr+aBD[minor]);
!       sizetomap -= arg;
! 
!       image_ba[minor] = (char *)ioremap(arg,sizetomap);
!       if(!image_ba[minor]) {
!         OkToWrite[minor] = 0;     
!         return -1;
!       }
!       image_ptr[minor] = (int)image_ba[minor];
!       OkToWrite[minor] = 1;
  
!       // Calculate the VME Address
!       bs = readl(baseaddr+aBS[minor]);
!       to = readl(baseaddr+aTO[minor]);
!       image_va[minor]  = bs + to;
!       break;
! 
!     case IOCTL_SET_BD:
!       writel(arg,baseaddr+aBD[minor]);
!       break;  
!     case IOCTL_SET_TO:
!       writel(arg,baseaddr+aTO[minor]);
! 
!       // Calculate the VME Address
!       bs = readl(baseaddr+aBS[minor]);
!       to = readl(baseaddr+aTO[minor]);
!       image_va[minor]  = bs + to;
!       break;  
!     default:
!       if(cmd < 0x1000) {  // This is a Register value so write to it.
!         writel(arg,baseaddr+cmd);
!       }
!       break;  
    }
    return(0);
  }
--- 609,670 ----
    unsigned int sizetomap = 0, to = 0, bs = 0;
  
    ioctls++;
!   switch (cmd) {
!   case IOCTL_SET_CTL:
!     writel(arg,baseaddr+aCTL[minor]);
! 
!     // Lets compute and save the DMA CTL Register
!     DMA[minor] = arg & 0x00FFFF00;
!     break;
! 
!   case IOCTL_SET_MODE:
!     mode[minor] = arg;
!     break;        
! 
!     // Lets Map the VME Bus to the PCI Bus
!     //
!     // << NOTE >> BD Must already be set before you call this!!!!
!     //
!     //
!   case IOCTL_SET_BS:
!     writel(arg,baseaddr+aBS[minor]);
!     if (image_ba[minor])
!       iounmap(image_ba[minor]);
! 
!     // This uses the BD Register to Find the size of the Image Mapping		
!     sizetomap = readl(baseaddr+aBD[minor]);
!     sizetomap -= arg;
! 
!     image_ba[minor] = (char *)ioremap(arg,sizetomap);
!     if (!image_ba[minor]) {
!       OkToWrite[minor] = 0;     
!       return -1;
!     }
!     image_ptr[minor] = (int)image_ba[minor];
!     OkToWrite[minor] = 1;
  
!     // Calculate the VME Address
!     bs = readl(baseaddr+aBS[minor]);
!     to = readl(baseaddr+aTO[minor]);
!     image_va[minor]  = bs + to;
!     break;
! 
!   case IOCTL_SET_BD:
!     writel(arg,baseaddr+aBD[minor]);
!     break;  
!   case IOCTL_SET_TO:
!     writel(arg,baseaddr+aTO[minor]);
! 
!     // Calculate the VME Address
!     bs = readl(baseaddr+aBS[minor]);
!     to = readl(baseaddr+aTO[minor]);
!     image_va[minor]  = bs + to;
!     break;  
!   default:
!     if (cmd < 0x1000) {  // This is a Register value so write to it.
!       writel(arg,baseaddr+cmd);
!     }
!     break;  
    }
    return(0);
  }
***************
*** 683,689 ****
    int x = 0;
    int done = 0;
  
!   while(!done && (x < 10)) {
      x++;
      sprintf(buff,"<ca91c042> (%i) dctl=%08X, dtbc=%08X\n",x,p->dctl,p->dtbc);
      printk(buff);
--- 684,690 ----
    int x = 0;
    int done = 0;
  
!   while (!done && (x < 10)) {
      x++;
      sprintf(buff,"<ca91c042> (%i) dctl=%08X, dtbc=%08X\n",x,p->dctl,p->dtbc);
      printk(buff);
***************
*** 708,714 ****
  {
    printk("<<ca91c042>> DMA Timed out\n");
  
!   if(DMACallBackFunc)
      DMACallBackFunc(1);
    DMACallBackFunc = NULL;
  }
--- 709,715 ----
  {
    printk("<<ca91c042>> DMA Timed out\n");
  
!   if (DMACallBackFunc)
      DMACallBackFunc(1);
    DMACallBackFunc = NULL;
  }
***************
*** 732,738 ****
  
    val = readl(baseaddr+DGCS);
  
!   if(!(val & 0x00000800)) {
      sprintf(buf,"<<ca91c042>> DMA Error in DMA_irq_handler DGCS=%08X\n",val);  
      printk(buf);
      val = readl(baseaddr+DCPP);
--- 733,739 ----
  
    val = readl(baseaddr+DGCS);
  
!   if (!(val & 0x00000800)) {
      sprintf(buf,"<<ca91c042>> DMA Error in DMA_irq_handler DGCS=%08X\n",val);  
      printk(buf);
      val = readl(baseaddr+DCPP);
***************
*** 751,757 ****
      sprintf(buf,"<<ca91c042>> DVA=%08X\n",val);  
      printk(buf);
  
!     if(DMAType == DMATYPE_LLIST) {
        printk("<<ca91c042>> CmdPacketList sent to DMARead\n");
        PrintCmdPacketList(debugptr);
  
--- 752,758 ----
      sprintf(buf,"<<ca91c042>> DVA=%08X\n",val);  
      printk(buf);
  
!     if (DMAType == DMATYPE_LLIST) {
        printk("<<ca91c042>> CmdPacketList sent to DMARead\n");
        PrintCmdPacketList(debugptr);
  
***************
*** 764,770 ****
      cbv = 1;  // Call Back value is set to 1 to show error condition
    }
  
!   if(DMACallBackFunc)
      DMACallBackFunc(cbv);
  
    // We are done with the Call Back so clear it
--- 765,771 ----
      cbv = 1;  // Call Back value is set to 1 to show error condition
    }
  
!   if (DMACallBackFunc)
      DMACallBackFunc(cbv);
  
    // We are done with the Call Back so clear it
***************
*** 789,799 ****
  
    val = readl(baseaddr+DGCS);
  
!   if(!(val & 0x00000800)) {
      sprintf(buf,"<<ca91c042>> LERR_irq_handler DMA Read Error DGCS=%08X\n",val);  
      printk(buf);
  
!     if(DMAType == DMATYPE_LLIST) {
        cpl = (TDMA_Cmd_Packet*)readl(baseaddr+DCPP);   // Command Packet Pointer
        cpl = (TDMA_Cmd_Packet*)((int)cpl & ~0x03);
        PrintCmdPacketList(cpl);
--- 790,800 ----
  
    val = readl(baseaddr+DGCS);
  
!   if (!(val & 0x00000800)) {
      sprintf(buf,"<<ca91c042>> LERR_irq_handler DMA Read Error DGCS=%08X\n",val);  
      printk(buf);
  
!     if (DMAType == DMATYPE_LLIST) {
        cpl = (TDMA_Cmd_Packet*)readl(baseaddr+DCPP);   // Command Packet Pointer
        cpl = (TDMA_Cmd_Packet*)((int)cpl & ~0x03);
        PrintCmdPacketList(cpl);
***************
*** 803,809 ****
      }
    }
  
!   if(DMACallBackFunc)
      DMACallBackFunc(1);
    DMACallBackFunc = NULL;
  }
--- 804,810 ----
      }
    }
  
!   if (DMACallBackFunc)
      DMACallBackFunc(1);
    DMACallBackFunc = NULL;
  }
***************
*** 826,836 ****
  
    val = readl(baseaddr+DGCS);
  
!   if(!(val & 0x00000800)) {
      sprintf(buf,"<<ca91c042>> VERR_irq_handler DMA Read Error DGCS=%08X\n",val);  
      printk(buf);
  
!     if(DMAType == DMATYPE_LLIST) {
        cpl = (TDMA_Cmd_Packet*)readl(baseaddr+DCPP);   // Command Packet Pointer
        cpl = (TDMA_Cmd_Packet*)((int)cpl & ~0x03);
  
--- 827,837 ----
  
    val = readl(baseaddr+DGCS);
  
!   if (!(val & 0x00000800)) {
      sprintf(buf,"<<ca91c042>> VERR_irq_handler DMA Read Error DGCS=%08X\n",val);  
      printk(buf);
  
!     if (DMAType == DMATYPE_LLIST) {
        cpl = (TDMA_Cmd_Packet*)readl(baseaddr+DCPP);   // Command Packet Pointer
        cpl = (TDMA_Cmd_Packet*)((int)cpl & ~0x03);
  
***************
*** 841,847 ****
      }
    }
  
!   if(DMACallBackFunc)
      DMACallBackFunc(1);
    DMACallBackFunc = NULL;
  }
--- 842,848 ----
      }
    }
  
!   if (DMACallBackFunc)
      DMACallBackFunc(1);
    DMACallBackFunc = NULL;
  }
***************
*** 861,877 ****
    enable = readl(baseaddr+LINT_EN);
    stat = readl(baseaddr+LINT_STAT);
  
!   if(stat & 0x0100)
      DMA_irq_handler();
!   if(stat & 0x0200)
      LERR_irq_handler();
!   if(stat & 0x0400)
      VERR_irq_handler();
  
!   for(i=0;i<7;i++) {
      vector = readl(baseaddr+vmevec[i]);
!     if(stat & vmeirqbit[i] & enable) {
!       if(vmeirqs[i] != NULL) {
          vmeirqs[i](i+1, vector, dev_id, regs);
        }
      }
--- 862,878 ----
    enable = readl(baseaddr+LINT_EN);
    stat = readl(baseaddr+LINT_STAT);
  
!   if (stat & 0x0100)
      DMA_irq_handler();
!   if (stat & 0x0200)
      LERR_irq_handler();
!   if (stat & 0x0400)
      VERR_irq_handler();
  
!   for (i=0;i<7;i++) {
      vector = readl(baseaddr+vmevec[i]);
!     if (stat & vmeirqbit[i] & enable) {
!       if (vmeirqs[i] != NULL) {
          vmeirqs[i](i+1, vector, dev_id, regs);
        }
      }
***************
*** 897,904 ****
    pcivector = readl(baseaddr+PCI_MISC1) & 0x000000FF; 
    free_irq(pcivector,NULL);             // Free Vector
  
!   for(x=1;x<MAX_MINOR+1;x++) {
!     if(image_ba[x])
        iounmap(image_ba[x]);
    }    
    iounmap(baseaddr);
--- 898,905 ----
    pcivector = readl(baseaddr+PCI_MISC1) & 0x000000FF; 
    free_irq(pcivector,NULL);             // Free Vector
  
!   for (x=1;x<MAX_MINOR+1;x++) {
!     if (image_ba[x])
        iounmap(image_ba[x]);
    }    
    iounmap(baseaddr);
***************
*** 919,929 ****
  
    sprintf(vstr,"Tundra Universe PCI-VME Bridge Driver %s\n",Version);
    printk(vstr);
!   printk("  Copyright 1997-2000, Michael J. Wyrick\n");
  
!   if((uni_pci_dev = pci_find_device(PCI_VENDOR_ID_TUNDRA,
!                                     PCI_DEVICE_ID_TUNDRA_CA91C042, 
!                                     uni_pci_dev))) {
      printk("  Universe device found.");
  
      // Lets turn Latency off
--- 920,930 ----
  
    sprintf(vstr,"Tundra Universe PCI-VME Bridge Driver %s\n",Version);
    printk(vstr);
!   printk("  Copyright 1997-2001, Michael J. Wyrick\n");
  
!   if ((uni_pci_dev = pci_find_device(PCI_VENDOR_ID_TUNDRA,
!                                      PCI_DEVICE_ID_TUNDRA_CA91C042, 
!                                      uni_pci_dev))) {
      printk("  Universe device found.");
  
      // Lets turn Latency off
***************
*** 944,950 ****
      pci_write_config_dword(uni_pci_dev, PCI_BS, CONFIG_REG_SPACE);
      pci_read_config_dword(uni_pci_dev, PCI_BS, &ba);        
      baseaddr = (char *)ioremap(ba,4096);
!     if(!baseaddr) {
        printk("  vremap failed to map Universe to Kernel Space.\r");
        return 1;
      }
--- 945,951 ----
      pci_write_config_dword(uni_pci_dev, PCI_BS, CONFIG_REG_SPACE);
      pci_read_config_dword(uni_pci_dev, PCI_BS, &ba);        
      baseaddr = (char *)ioremap(ba,4096);
!     if (!baseaddr) {
        printk("  vremap failed to map Universe to Kernel Space.\r");
        return 1;
      }
***************
*** 952,958 ****
      // Check to see if the Mapping Worked out
      temp = readl(baseaddr);
      printk("  Read via mapping, PCI_ID = %08X\n",temp);       
!     if(temp != 0x000010E3) {
        printk("  Universe Chip Failed to Return PCI_ID in Memory Map.\n");
        return 1;
      }
--- 953,959 ----
      // Check to see if the Mapping Worked out
      temp = readl(baseaddr);
      printk("  Read via mapping, PCI_ID = %08X\n",temp);       
!     if (temp != 0x000010E3) {
        printk("  Universe Chip Failed to Return PCI_ID in Memory Map.\n");
        return 1;
      }
***************
*** 963,968 ****
--- 964,975 ----
      writel(0x00800000,baseaddr+LSI2_CTL);     
      writel(0x00800000,baseaddr+LSI3_CTL);     
  
+     // Write to Misc Register
+     // Set VME Bus Time-out
+     //   Arbitration Mode
+     //   DTACK Enable
+     writel(0x15060000,baseaddr+MISC_CTL);     
+ 
      // Lets turn off interrupts
      writel(0x00000000,baseaddr+LINT_EN);   // Disable interrupts in the Universe first
      writel(0x0000FFFF,baseaddr+LINT_STAT); // Clear Any Pending Interrupts
***************
*** 970,976 ****
      pci_read_config_dword(uni_pci_dev, PCI_INTERRUPT_LINE, &irq);
      irq &= 0x000000FF;                    // Only a byte in size
      result = request_irq(irq, irq_handler, SA_INTERRUPT, "VMEBus (ca91c042)", NULL);
!     if(result) {
        printk("  ca91c042: can't get assigned pci irq vector %02X\n", irq);
      } else {
        writel(0x0000, baseaddr+LINT_MAP0);    // Map all ints to 0
--- 977,983 ----
      pci_read_config_dword(uni_pci_dev, PCI_INTERRUPT_LINE, &irq);
      irq &= 0x000000FF;                    // Only a byte in size
      result = request_irq(irq, irq_handler, SA_INTERRUPT, "VMEBus (ca91c042)", NULL);
!     if (result) {
        printk("  ca91c042: can't get assigned pci irq vector %02X\n", irq);
      } else {
        writel(0x0000, baseaddr+LINT_MAP0);    // Map all ints to 0
***************
*** 982,988 ****
      return 1;
    }
  
!   if(register_chrdev(UNI_MAJOR, "uni", &uni_fops)) {
      printk("  Error getting Major Number for Drivers\n");
      iounmap(baseaddr);
      return(1);
--- 989,995 ----
      return 1;
    }
  
!   if (register_chrdev(UNI_MAJOR, "uni", &uni_fops)) {
      printk("  Error getting Major Number for Drivers\n");
      iounmap(baseaddr);
      return(1);
***************
*** 992,998 ****
  
    register_proc();
  
!   for(x=0;x<MAX_MINOR+1;x++) {
      image_ba[x]  = 0;               // Not defined
      image_ptr[x] = 0;               // Not defined
      opened[x]    = 0;               // Closed
--- 999,1005 ----
  
    register_proc();
  
!   for (x=0;x<MAX_MINOR+1;x++) {
      image_ba[x]  = 0;               // Not defined
      image_ptr[x] = 0;               // Not defined
      opened[x]    = 0;               // Closed
***************
*** 1086,1093 ****
  //-----------------------------------------------------------------------------
  int request_vmeirq(unsigned int irq, TirqHandler handler)
  {
!   if((irq >= 1) && (irq <= 7)) {
!     if(vmeirqs[irq-1] == NULL) {
        vmeirqs[irq-1] = handler;
        return 0;
      }
--- 1093,1100 ----
  //-----------------------------------------------------------------------------
  int request_vmeirq(unsigned int irq, TirqHandler handler)
  {
!   if ((irq >= 1) && (irq <= 7)) {
!     if (vmeirqs[irq-1] == NULL) {
        vmeirqs[irq-1] = handler;
        return 0;
      }
***************
*** 1107,1113 ****
  //-----------------------------------------------------------------------------
  void free_vmeirq(unsigned int irq)
  {
!   if((irq >= 1) && (irq <= 7))
      vmeirqs[irq-1] = NULL;
  }
  
--- 1114,1120 ----
  //-----------------------------------------------------------------------------
  void free_vmeirq(unsigned int irq)
  {
!   if ((irq >= 1) && (irq <= 7))
      vmeirqs[irq-1] = NULL;
  }
  
***************
*** 1129,1136 ****
    char *ptr;
    unsigned int to;
  
!   if((image >=0) && (image <=3)) {
!     if((pci >= 0xB0000000) && (pci <= 0xE0000000)) {
        to = vme-pci;
        // Setup the Mapping in the Universe
        writel(pci, baseaddr + aBS[image]);
--- 1136,1143 ----
    char *ptr;
    unsigned int to;
  
!   if ((image >=0) && (image <=3)) {
!     if ((pci >= 0xB0000000) && (pci <= 0xE0000000)) {
        to = vme-pci;
        // Setup the Mapping in the Universe
        writel(pci, baseaddr + aBS[image]);
***************
*** 1140,1146 ****
  
        // Get the Virtual address of the PCI Address map
        ptr = (char *)ioremap(pci,size);
!       if(ptr == NULL) {
          printk("<ca91c042> ioremap failed in mapvme\n");
          return NULL;
        } else {
--- 1147,1153 ----
  
        // Get the Virtual address of the PCI Address map
        ptr = (char *)ioremap(pci,size);
!       if (ptr == NULL) {
          printk("<ca91c042> ioremap failed in mapvme\n");
          return NULL;
        } else {
***************
*** 1161,1167 ****
  //-----------------------------------------------------------------------------
  void unmapvme(char *ptr, int image)
  {
!   if((image >= 0) && (image <=3)) {
      // Clear the Mapping in the Universe
      writel(0x00000000, baseaddr + aCTL[image]);
      writel(0x00000000, baseaddr + aBS[image]);
--- 1168,1174 ----
  //-----------------------------------------------------------------------------
  void unmapvme(char *ptr, int image)
  {
!   if ((image >= 0) && (image <=3)) {
      // Clear the Mapping in the Universe
      writel(0x00000000, baseaddr + aCTL[image]);
      writel(0x00000000, baseaddr + aBS[image]);
***************
*** 1249,1252 ****
--- 1256,1275 ----
    // sleep or what ever until the DMA is done
  }
  
+ //-----------------------------------------------------------------------------
+ // Function   : VME_Bus_Error
+ // Inputs     : 
+ // Outputs    : 
+ // Description: Returns 1 if a Bus Error is Pending
+ // Remarks    : 
+ // History    : 10/30/2000 mjw Started
+ //-------------------------------------------------------------------------mjw-
+ int VME_Bus_Error(void)
+ {
+   int pci_csr;
+ 
+   pci_csr = readl(baseaddr+PCI_CSR);           // Check for Bus Error
+   writel(pci_csr,baseaddr+PCI_CSR);            // Clear the Error
+   return((pci_csr & 0x08000000) ? 1 : 0);
+ }
  

 

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